Sega 32X Manuál

132XHardware ManualDoc. #MAR-32-R4-072294

101.2. 32X Block Diagram32X is made up of the following parts (see Figure 2.1)- MEGA Drive I/F Component (I/F chipbuilt-in)- 32X Cartridge- SH2 Co

100move.w #$ff,$4(a1) ; Fill Length Reg.fill0:move.w d1,$6(a1) ; Fill Start Address Reg.move.w d0,$8(a1) ; Fill Data Reg.nopfen0:btst.b #1,$b(a1) ; FE

101* ---- Communication Reg. Clearmoveq #0,d0move.l d0,$20(a1) ; clear "M_OK"move.l d0,$24(a1) ; clear "S_OK"move.b #3,$5101(a5) ;

102bne MarsErrortvmodeok:* ---- CheckSum Comparemoveq #$20,d0lea $880000,a0 ; MARS Bank Image Addressmove.w $18e(a0),d6 ; CheckSum Datatst.w d6beq ck

111.3. About the 32X BlockThe role and features of each 32X block shown in section 2.1 is explained below. Seechapter 3 for more information.MEGA Dri

12SDRAM ComponentThe 32X has 2Mbits of SDRAM (synchronous DRAM) as its main memory for the SH2chips. The SH2 program on the cartridge ROM is loaded in

13Color Palette ComponentThe color palette is a 256 word RAM block. When in the packed pixel mode or run lengthmode, pixel data in the frame buffer se

143. Functions

151.4. MappingThe 32x hardware can be controlled from both the main CPU SH2 and MEGA Drive68000. As stated in the last chapter, the layout of each bl

16ROM Access when using the 32XThe 68000 vector area (00 0000h - 00 00FFh) is assigned by the custom built-in ROM.Because the ROM contents are 88 0200

17SH2 Memory MapThe 32X has two SH2 chips mounted to a common bus. Consequently, memory maps ofthe two chips shown in Figure 3.2 are the same. The SH2

18Cache Area AccessCache memory is memory used for rapidly supplying commands, operans, and data to theCPU. The 32X accesses the cache after commands

191.5. Registers32X registers are classified ad shown below. Meanings of the address and set value of eachregister are also shown.32X System Register

2HistoryProvisional Version 1:(May 11, 1994)Introduction, Section 1 - 3.4, 6.2, 6.3Total 64 pagesProvisional Version 2:(May 23, 1994)Sections 3.5, 4.1

20VDP registerDisplay mode selectionBitmap Mode registerFrame buffer switchFrame buffer cotnrol registerScreen shiftScreen shift control registerData

21System Registers[MEGA Drive side]Using the 32XAdapter Control Register (Access : Byte/Word)Bit1514131211109876543210MD SideR/WRead onlyR/WR/WA1 5100

22Interrupt issued for SH2Interrupt Control Register (Access : Byte/Word)Bit1514131211109876543210MD SideR/WR/WA1 5102h--------------INTSINTMINTS: Sla

23Transfers Data to SH2 DMACTransfers Data to SH2 DMAC(Access : Byte/Word)Bit1514131211109876543210MD SideRead onlyR/WR/WR/WA1 5106h--------FULL----68

2468K to SH DREQ Destination Address Register(Acces : Word)Bit1514131211109876543210MD SideR/WA1 510Ch-High OrderA1 510EhLow Order0Sets the SH2 side (

25Refresh Singal Output to CartridgeSEGA TV Register (Acces: Byte/Word)Bit1514131211109876543210MD SideR/WA1 511Ah---------------CMCM: Cartridge Mode0

26PWM Sound Source ControlPWM Control Register (Access: Byte/Word)Bit1514131211109876543210MD SideRead onlyR/WR/WR/WR/WA1 5130h----TM3TM2TM1TM0RTP---R

27L ch Pulse Width Register(Access : Byte/Word)Bit1514131211109876543210MD SideRead onlyWrite onlyA1 5134hFULLEMPTY-- The value set by bit 11~0 x Scyc

28[SH2 side]Interrupt Control for SH2Interrupt Mask Register (Access : Byte/Word)Bit1514131211109876543210SH SideRead onlyR/WR/WR/WR/WR/W2000 4000hFM-

29H Count Register(Access : Byte/Word)Bit1514131211109876543210SH SideR/W2000 4004h- Sets H int occurrence interval. Designates byt the number

3IntroductionThis manual applis to the development of game software and explains power up booster "32X"hardware functions for the MEGA Drive

30PWM Interrupt Clear Register(Access : Word)Bit1514131211109876543210SH SideWrite only2000 401Ch Clears PWM interrupt (command interru

31Points to be aware of concerning interrputEx. 1. 32X has VRESINT, VINT, HINT, CMDINT and PWMINT, but amongthese, only CMDINT has points which diffe

32Activating the 32X Custom ComponentStandBy Changer Register (Access : Word)Bit1514131211109876543210SH SideWrite only2000 4002h Use w

3368k to SH DREQ Length Register(Access : Word)Bit1514131211109876543210SH SideRead only2000 4010h 00See explanation of MEGA Drive regist

34PWM Sound Source ControlPWM Control Register (Access : Byte/Word)Bit1514131211109876543210SH SideR/WR/WR/WR/WR/WR/WR/WR/WR/W2000 4030h----TM3TM2TM1T

35

36VDP Registers(Both MEGA Drive and SH2 Common)Display mode SelectionBitmap Mode Register(Access : Byte/Word)1514131211109876543210Read onlyR/WR/WR/WR

37Frame Buffer SwitchingFrame Buffer Control Register(Access : Byte/Word)1514131211109876543210MD SideA1 518AhRead onlyR/WR/WSH Side2000 410AhVBLKHBLK

38Screen ShiftScreen Shift Control Register(Access : Byte/Word)1514131211109876543210MD SideA1 5182hR/WSH Side2000 4102h---------------SFTSFT: Screen

391.6. VDP32X VDP (referred to as VDP thereafter) controls the color display and has two 1 Mbitframe buffer surfaces for control display screens. Dis

4TerminologyRISC (Reduced Instruction Set Computer)This computer architecture improves performance by simplifying instructionsspecifications and has s

40Display ModeEnables output of images that correspond to the NTSC format (Japan, USA) and the PALformat (Western Europe). When the 32X image output i

41VDP ConfigurationVDP is mapped, as shown below, from SH2 address 2000 4100h and 2400 0000h. Theseexist as I/O devices for the CPU. As a resulte, acc

42Switching Frame BuffersBy switching the FS bit, the DRAM draw previously handled by the CPU is transferred tothe VDP and the contents are displayed.

431514131211109876543210Read onlyR/WR/WSH Side2000 410AhVBLKHBLKPEN-----------FENFSFS = 0SH (Cache-through) DRAM0Display2400 0000h DrawDRAM1Mbit 1M

44Color PaletteThere is one DRAM0 and DRAM1 common color palette in the 32X, and 0~255 palettecode can be specified per each pixel. The figure belows

45Over Write ImageAllows RAM block that is physically identical to the DRAM area to be accessed from thisarea. When writing data from this area, data

46Overview of Display SpecificationsDisplay Size320 pixels x 224 pixels or 320 pixels x 240 pixelsonly the non-interlace modeDisplay Colors32 768 colo

47Line Table FormatThere are 256 words in the line table in the frame buffer lead. When writing an address inwhich pixel data for each line is entered

48PrioritySelect whether or not to use the PRI bit of the VDP register, and whether the 32X is to bedisplayed in front of or behind the MD screen. Als

49Direct Color ModeThis mode directly expresses data of each line from the pixel in the left corner of thescreen by each through bit B, G, R (16-bit).

5Contents1. Introduction to 32X ...

50Packed Pixel ModeThis mode indirectly expresses data of each line by individual color palette codes (8-bit)from pixels in the left corner of the scr

51Screen Shift ControlBecause of word units, address data that can be set in the ne table can change the tableonly in 2-dot units when in the packed p

52Run Length ModeIn this mode, pixel data is handled in units as the same colors that continue horizontally,and is represented in palette code (8-bit)

53FILL FunctionAuto Fill uses three registers : the start address, word length, and file data. VDP beginsthe fill operation when writing to the file d

54Clock Used by the 32XThe master clocks for NTSC and PAL used by the MEGA Drive and 32X are diffferent.The 68000 and SH2 system clocks are shown belo

55HBlank and Display PeriodsFigure 3.15 HBLANK Period and Display PeriodA: Blank Period 100 dot (860 Mck)B: Display Period 320 dot (2560 Mck)C: HBLANK

56VDP Register Latch TimingFigure 3.17 VDP Register Latch TimingA: H Blank - PEN 3 dot (24 Mck)B: FEN Width 40 Sclk (VDP side refresh)C: H Blank - lat

571.7. PWMPWM Sound Sound Source32X outputs a 2 ch pusle wave as a sound source. The integrated wave form converts thepulse width to wave height. A v

58Functions of 32X PWMThere are five registers within the SYS REG are for controlling PWM of the 32X (seesection 3.2). It is possible to access from b

59Cycle and Pulse Width SettingsBoth the cycle and pulse width are 12-bit and can be set from 0 to 4095.The cycle register obtains the required sampli

61.15. Restrictions ...

601.8. SH2SH2 is a RISC (Reduced Instruction Set Computer) type processor. As with other RISCtype processors, it has the following features due to it

61Reduced Cycle Time (Increased Clock Speed)Internal operations can be made faster if the clock speed of the processor is increased, buta gap is creat

62Master and SlaveTwo SH2 units are packaged on a common external bus in the 32X. SDRAM and 32Xhardware resources are connected to this bus and access

63CacheSH2 contains 4-Kbyte cache memory. Since this memory is accessed per 1 cycle, it iseffectively executed by reducing the wait states during acce

64Cache OverviewIn SH2, address bit 3~0 is called an intra-line byte address, and the cache handles addressspace from the lead (0000 0000h) in line un

65

66Cache after implemtenig BOOT ROMThe BOOT ROM mounted in the 32X, both master and slave, purges (initializes) andenables the cache immediately after

67DMASH2 contains a 2 channel DMA. If transfer request is set to auto request and is within theSH2 address space, transfer betwwen memories can be per

68Master-Slave CommunicationWhen communicating for coordination between the master and slave, it is important toknow how to properly receive data and

6968000-SH2 CommunicationFigure 3.28 68000 and SH2 CommunicationCommunication PortThe 32X has an 8 word register that can read and write from both &qu

71. Introduction to 32X

70DMASH2 has a 2 channel DMA built-in to it. When the 32X uses channel 0 from among thetwo channels, data can be transferred from the MEGA Drive side

71InterruptThere are five ways an interrupt can be created :- pressing the MEGA Drive reset button- during vertical feedback- during horizontal fee

724. 32X Block Access

731.9. 32X Block Access by SH2Blocks that Can Be Directly AccessedAccess from SH2, 68000, and Z80 to all 32X buffer registers corresponds to the list

74Cache-through AccessSystem and VDP registers must be accessed by cache-through. Although system designalso allows access by cache, because there is

751.10. 32X Block Access by 68000Blocks that can be directly accessedAfter the power is turned on, address space of 68000 is mapped the same as the M

761.11. 32X Block Access by Z80Blocks that can be directly accessedZ80 is laoded as the MEGA Drive sound CPU. Event when 32X is mapping in the 68000a

771.12. Access Timing of each CPU to 32X BlockThe timing sequence when the CPU accesses the peripheral is called a bus cycle, andtakes a minimum of 4

78VDP RegisterSH2 (Read/Write): 5 wait (const)68K (Read): 2 wait (const)68K (Write): 0 wait (const)System RegisterSH2 (Read/Write): 1 wait (const)68K

795. Other

81.1. Introduction to 32XThe 32X is a power-up booster installed in the MEGA Drive cartridge slot. This adds abitmap screen of up to 32,768 simultane

801.13. Boot ROMThe Boot ROM is an SH2 execution object that is loaded in 32X as ROM, and is differentin content with respect to the master CPU and s

81Mega Drive and SH2 SynchronizationThe Boot ROM flow chart is shown in Figure 5.2. The "comm 0, 4, 8" reference in thefigure below refers t

82Figure 5.3 Boot ROM Flow Chart (Slave)Boot (Master)General PurposeRegister InitializationBus StateController InitializationsleepCustom ClearCache ON

831.14. SecurityInitial ProgramThe Initial program performs hardware security and everything required upon resetting inorder to equalize all hardwar

84Included in the Initial ProgramA list of the Mega Drive side sample program is shown in Figure 5.4 below. The initialprogram (ICD_MARS.PRG) appears

851.15. Restrictions1. When performing SH2 auto request DMA, both master interrupt and slaveinterrupt must be masked. If DMA is performed by both ma

86Please make the following setting in response to use when transferring with DMAC ofSH2.1. Transfer from DREQ FIFO to memory (channel 0 is used by e

87Restrictions Concerning SH2 InterruptThe 32X SH2 has five types of interrupt.Level 14 VRES interruptLevel 12 V interruptLevel 10 H interruptLevel 8

886. Annexes

891.16. Master Boot ROMorg $0* VBRdc.l reset ; 0: POWER ON RESET PCdc.l 0x06040000 ; 1: POWER ON RESER SPdc.l reset ; 2: MANUAL RESET PCdc.l 0x060400

92. Configuration

90GPRInit:0x00000144: 0xE000 mov #0x00, r00x00000146: 0xE100 mov #0x00, r10x00000148: 0xE200 mov #0x00, r20x0000014A: 0xE300 mov #0x00, r30x0000014C:

91Register0x000001B6: 0xE000 mov #0x00, r00x000001B8: 0x2800 mov.b r0, @r80x000001BA: 0xD95B mov.l @(0x170, pc), r9 ; 0x00000328, r9 = $FFFFFE92 Cache

920x00000228: 0xDB06 mov.l @(0x01C, pc), r11 ; 0x00000244, r11 = $0000076CInitialProgramCheck:0x0000022A: 0x67C5 mov.w @r12+, r7 ; r7 = $46FC, r12 = $

930x000002A2: 0x8BF9 bf 0x000002980x000002A4: 0x50D2 mov.l @(0x008, r13), r0 ; r0 = Master SH2 VBR from cartridge0x000002A6: 0x402E ldc r0, vbr0x00000

94dc.l $0001FFE0dc.l $26000000dc.l $26040000dc.l $A55A0001dc.l $A55A00A8dc.l $A55A0055dc.l $A55A0AB8dc.l $A55A0008dc.l $A55A0000dc.l $A55A0059dc.l $FF

951.17. Initial program* DIAGNSTC\SOURCE\MD\SOURCE****************************************************************** MARS Initial & Security ( Ca

96** Mega Drive / Genesis Initialize* MARS System Register Initialize* MARS VDP Register Initialize* MARS Frame Buffer Clear* SH2 SDRAM Clear & Pr

97beq.b cold_start ; reset hot_startbtst.b #0,$5101(a5) ; check adapter modebne Hot_Start* power on (cold_start)cold_start:* ---- Securitymove.b 1(a5)

98z80_prg:dc.b $AF ;XOR Adc.b $01,$D9,$1F ;LD BC,1FD9Hdc.b $11,$27,$00 ;LD DE,0027Hdc.b $21,$26,$00 ;LD HL,0026Hdc.b $F9 ;LD SP,HLdc.b $77 ;LD (HL),Ad

99VramClear:movem.l d0/d7/a0/a1,-(a7)* dc.l $48e781c0lea fill_data,a0lea $c00004,a1move.w (a0)+,(a1)move.w (a0)+,(a1)move.w (a0)+,(a1)move.w (a0)+,(a1